1. Technical Field
The present disclosure relates to a method of fabricating an integrated circuit of CMOS technology in a semiconductor wafer comprising scribe lines.
2. Description of the Related Art
FIG. 1 shows a conventional method of fabricating an integrated circuit IC1. Integrated circuits IC1 are collectively made in a semiconductor wafer 20 comprising scribe lines 21, 22 separating each integrated circuit IC1. Integrated circuit IC1 comprises a semiconductor substrate 10, a circuit region 11 embedded in substrate 10, and contact pads P1, P2, P3, P4, P5. Circuit region 11, schematically shown by a dashed rectangle, comprises active components such as transistors, and may also comprise passive components such as resistors, diodes, etc. It also comprises conductors separated by layers of dielectric material. These conductors link different parts of circuit region 11 and also link the inputs or outputs of the circuit region to contact pads P1 to P5, which extend over the front side of the wafer, not within scribe lines 21, 22. Pad P5 is a ground contact pad electrically linked to substrate 10 and to circuit region 11.
Integrated circuit IC1 is then individualized by cutting the wafer 20 in the scribe lines 21, 22, in a process known as “singulation”. The integrated circuit is then arranged in an interconnection package 30, as shown in FIG. 2. Package 30 comprises conductive leads 31 and a ground plane 32 on which the back side of integrated circuit IC1 is fixed, by the intermediary of a conductive material of the conductive glue or solder type. Contact pads P1 to P5 are then linked to conductive leads 31-1 to 31-5 of the package 30 by means of conductive wires W1 to W5. Leads 31 are destined to be soldered on an interconnection support, for example a printed circuit, lead 31-5 being linked to pad P5 and acting as a ground lead.
Such an integrated circuit is generally made using CMOS (Complementary Metal Oxide Semiconductor) technology, and circuit region 11 comprises NMOS transistors (N channel transistors) and PMOS transistors (P channel transistors). This technology allows substrate 10 to be electrically linked with a very low series resistance to circuit region 11, by the intermediary of internal connections in doped silicon. It is generally not necessary therefore to link the back side of the integrated circuit to ground pad P5 by means of an external connection, as it was the case with NMOS technology integrated circuits (a technology no longer in use). NMOS integrated circuits comprised a ground contact pad on their back side which needed to be linked to ground pad P5 by the exterior of the integrated circuit, so that substrate 10 could be brought to the same ground potential as circuit region 11. As shown in FIG. 2, a contact pad C1 was generally provided on ground plane 32 of the package, which was connected by means of a conductive wire W6 to lead 31-5. The back side of the integrated circuit was generally covered by a conductive layer, for example gold, to ensure a good electrical contact with ground plane 32.
In certain applications, integrated circuit IC1 is a very simple structure and circuit region 11 has a small surface area. In this case, the surface occupied by the different contact pads P1 to P5 on the front side of the integrated circuit may turn out to be as large as the surface area occupied by circuit region 11.
It may therefore be desired to reduce the surface area occupied by the contact pads, in order to reduce the overall size of the integrated circuit and to be able to make a greater number of integrated circuits IC1 on a given semiconductor wafer surface area.
Nevertheless, the surface area occupied by scribe lines 21, 22 cannot be reduced and is imposed by the singulation technique used (saw, laser, . . . ). Similarly, the surface area of contact pads P1 to P5 cannot be reduced and is imposed by the connection technique of pads P1 to P5 to the leads 31 of the package, in general a an ultrasonic solder wiring technique.
To reduce the surface area occupied by contact pads P1 to P5, the present disclosure is based on the observation that the ground pad P5 could be removed in a CMOS technology integrated circuit, and be replaced by a ground contact on the back side. Indeed, the weak series resistance between circuit region 11 and substrate 10 may allow the application of the ground potential to circuit region 11 by the intermediary of the back side of the integrated circuit, that is, by the intermediary of the substrate, to reach pad P5.
Nevertheless, ground pad P5 is used during a test phase of integrated circuit IC1, when it is still on wafer 20. This test phase conventionally uses a probe card applied to the front side of the wafer. Ground pad P5 is therefore used for the electrical test of the integrated circuit before the singulation of the wafer.